1. Field of the Invention
The AC-type PDPs can be grouped into those of the two electrode type which effect the selective discharge (address discharge) and sustain discharge using two electrodes and those of the three electrode type which effect the address discharge using a third electrode.
In the color PDP that effects the gradation display, the fluorescent material formed in the discharge cell is excited by ultraviolet rays generated by an electric discharge. The fluorescent material, however, is not resistant to the bombardment of ions which create a positive charge generated by the electric discharge. In the two-electrode type device in which the ions directly hit upon the fluorescent material, it is likely that the fluorescent material has a short life.
In order to avoid this, the color PDP usually employs a three-electrode structure utilizing surface discharge. Even the three electrode-type devices can be grouped into those in which the third electrode is formed on a substrate on which are arranged the first and second electrodes for effecting the sustain discharge, and those in which the third electrode is disposed on another opposing substrate.
Moreover, the devices in which the three electrodes are formed on the same substrate can be further grouped into those in which the third electrode is arranged on the two electrodes that effect the sustain discharge, and those in which the third electrode is arranged under the two electrodes.
Furthermore, visible light emitted from the fluorescent material may be viewed through the fluorescent material (transmission type) or after it is reflected by the fluorescent material (reflection type). The cell that effects the electric discharge has been cut for its spatial linkage to the neighboring cell by a barrier wall (rib portion or barrier).
In another example, the barrier walls are provided on four sides to surround the discharging cell in a completely sealing manner, or the barrier walls are provided in one direction only; but in another direction, the spatial linkage between the discharging cell and the neighboring cell can be cut by normalizing a gap (distance) between the electrodes.
The present invention relates to a plasma display device (PDP) as explained above and to a driving method thereof.
2. Description of the Related Art
In this specification, the explanation about the present invention will be given utilizing a specific embodiment of a plasma display device 1 according to the present invention in which a third electrode (address electrode) is formed on a substrate which opposes a substrate of electrodes that effect the sustain discharge. In this plasma display device of the reflection type, the barrier wall is formed in the vertical direction only (i.e., at right angles with the first electrode which may be the X-electrode and the second electrode which may be the Y-electrode, and is in parallel with the third electrode), and the sustain electrode is partly constituted by a transparent electrode. It should, however, be noted that the present invention is in no way limited to the constitution of this embodiment only, and the technical features of the present invention can be applicable to all of the different kinds of plasma display panels.
FIG. 1 is a plan view which schematically illustrates the constitution of the PDP of the above-mentioned three-electrode surface-discharge type according to the embodiment, FIG. 2 is a sectional view (in the vertical direction) which schematically illustrates a discharge cell in the panel of FIG. 1, and FIG. 3 is a sectional view which schematically illustrates the discharge cell in a horizontal direction but at right angles with that of FIG. 2.
A panel 1 is constituted by two glass substrates 4 and 5. On the first substrate 4 are provided a first electrode, i.e., X-electrode XD and a second electrode, i.e., Y-electrode YD that are sustain electrodes 10 arranged in parallel. These electrodes XD and YD are constituted by a transparent electrode 9 and a bus electrode 8.
The transparent electrode 9 must permit the light 12 reflected by a fluorescent material 11 to pass through, and is composed of, for example, ITO (transparent conductor film composed chiefly of indium oxide) or the like. In order to prevent the voltage drop caused by the electrode resistance, furthermore, the bus electrode 8 must have a small resistance and is, hence, composed of Cr or Cu. These electrodes are further covered with a dielectric layer (glass) 7, and a MgO (magnesium oxide) film is formed as a protection film 6 on the discharge surface.
In the second substrate 5 opposing the first glass substrate 4 is formed a third electrode (address electrode) AD in a manner to be at right angles with the sustain electrodes 10. Furthermore, barrier walls 2 are formed between the address electrodes AD, and fluorescent materials 11 having red-, green- and blue-light emitting properties are arranged between the barrier walls 2 in a manner to cover the address electrodes AD.
The two glass substrates 4 and 5 are assembled in a manner that the ridges of the barrier walls 2 and the surface of the MgO film 6 are brought into intimate contact with each other.
Light-emitting cell portions 3 are formed near the intersecting points of the X- and Y-electrodes XD, TD and the address electrodes AD in a region surrounded by the barrier walls 2.
FIG. 4 is a block diagram which schematically illustrates peripheral circuits for driving the plasma display device (PDP) shown in FIGS. 1 and 2. Each address electrode AD is connected to the address driver 13 which applies an address pulse at the time of address discharge.
The Y-electrodes YD1 to YDn are each connected to a Y-scan driver 14 which is connected to a Y-side common driver 15. The Y-scan driver 14 generates a pulse at the time of address discharge, and a sustain pulse is generated by the Y-side common driver 15 and is applied to the Y-electrodes YD1 to YDn through the Y-scan driver 14.
The X-electrodes XD are connected and are taken out in common over the whole display lines of the panel 1.
An X-side common driver 16 generates a write pulse, a sustain pulse and like pulses. The driver circuit 16 is controlled by a control circuit 17.
The control circuit 17 is constituted by a display data control unit 18 that includes a frame memory 19, and a panel drive control unit 20 that includes a scan driver control unit 21 and a common driver control unit 22, and is controlled by synchronizing signals Vsync, Hsync and a display data signal DATA that are input from external units.
FIG. 5 is a diagram of waveforms according to a prior method of when the plasma display device (PDP) shown in FIGS. 1 to 3 is to be driven by a circuit shown in FIG. 4, and illustrates voltage waveforms on the electrodes during the period of a sub-field (SF) according to a conventional so-called "address/sustain discharge period separation-type write address system".
In this example, the sub-field SF is divided into a reset period S1 used for the initialization, an address period S2 and a sustain discharge period S3.
The reset period is used for executing the initializing operation such as for executing the total erasure, total self erasure and total writing and total self erasure.
Furthermore, since the period of one frame for displaying the screen has been roughly determined by the period of a vertical synchronizing signal Vsync, a quiescent period S4 of a predetermined length that can be varied is inevitably formed by a difference between one period of a vertical synchronizing signal and the sum of the reset period S1, the address period S2 and the sustain discharge period S3.
In the above-mentioned reset period S1, first, the Y-electrodes YD1 to YDn all assume a 0-V level and, at the same time, a total writing pulse of a voltage Vs+Vw (about 330 V) is applied to the X-electrodes XD. As a result, the electric discharge takes place in all cells of all display lines irrespective of the preceding display state.
In this case, the address electrode potential is about 100 V (Vaw). Then, the potential becomes 0 V at the X-electrode and the address electrode, and the voltage of the wall charge exceeds the discharge start voltage of all cells 3; i.e., the discharge takes place. Since there is no potential difference among the electrodes, no wall charge is formed by the discharge. That is, the discharge is a so-called self-erasing discharge in which a space charge is self-neutralized to terminate the discharge.
Due to the self-erasing discharge, all cells 3 in the panel 1 acquire a uniform state without a wall charge. The reset period S1 allows all of the cells to acquire the same state irrespective of the turn-on state of the preceding sub-field, and enables the next address (write) discharge to be stably carried out.
In the next address period S2, an address discharge is carried out in the order of lines to turn the cells 3 on and off depending upon the display data.
First, a scan pulse SCP of a -VY level (about minus 150 V) is applied to each of the Y-electrodes YD1 to YDn, an address pulse ADP of a voltage Va (about 50 V) is selectively applied to an address electrode ADn that corresponds to a cell 3 which is to effect sustain discharge, i.e., which is to be turned on, among the address electrodes AD1 to ADn, and the discharge is permitted to take place between the address electrode ADn of the cell 3 that is to be turned on and the Y-electrode YDn.
By using this discharging operation as a primer (igniting fire), an electric discharge is readily established between the X-electrodes XD (voltage Vx=50 V) and the Y-electrodes YD1 to YDn.
This enables the wall charge of an amount that causes sustain discharge to be accumulated in the MgO film 6 on the X-electrode XD of a selected cell of a selected line and on the Y-electrodes YD1 to YDn.
The same operation is carried out successively for other display lines, and the display data are newly written in all of the display lines.
Then, in the sustain discharge period S3, a sustain pulse SUSP having a voltage Vs (about 180 V) is alternately applied across the Y-electrodes YD1 to YDn and the X-electrodes to effect the sustain discharge, whereby the image of one sub-field is displayed.
That is, in the above-mentioned embodiment, a period in which a sustain pulse SUSP is alternately applied across the Y-electrode YDn and the X-electrode is called one cycle of the sustain discharge period.
In the plasma display device of the above-mentioned conventional address/sustain discharge separation type write address system, the brightness is determined depending upon the duration of the sustain discharge period S3, i.e., depending upon the number of the sustain pulses SUSP.
FIG. 6 illustrates a method of driving the plasma display device for effecting the multi-gradation display which, in this case, is a 256-gradation display.
In this embodiment, one frame is divided into eight sub-fields, i.e., SF1, SF2, SF3, SF4, SF5, SF6, SF7 and SF8.
In these sub-fields SF1 to SF8, the reset periods S1 and the address periods S2 have the same length.
The lengths of the sustain discharge periods comply with a ratio 1:2:4:8:16:32:64:128.
By selectively combining the sub-fields that are to be turned on, therefore, 256 stages of brightness can be displayed from 0 to 255.
Described below is a practical time sharing. If the screen is rewritten at 60 Hz, one frame lasts 16.6 ms (1/60 Hz). If the number of times of the sustain discharge cycles (sustain cycles) in one frame is 510 times, the numbers of sustain discharge cycles in each of the sub-fields are 2 cycles in SF1, 4 cycles in SF2, 8 cycles in SF3, 16 cycles in SF4, 32 cycles in SF5, 64 cycles in SF6, 128 cycles in SF7 and 256 cycles in SF8.
If the duration of the sustain discharge cycle is 8 .mu.s, then the total duration of one frame is 4.08 ms. Eight unit periods each comprising reset period S1 and address period S2, are assigned for a rest of duration of about 12 ms.
The reset period S1 is 50 .mu.s in each sub-field SF. Moreover, a time of 3 .mu.s is required for the address cycle (scan per a line). Therefore, if the panel has 480 display lines in the vertical direction, a time of 1.44 ms (3.times.480) is necessary.
In the above-mentioned conventional AC-type plasma display device (PDP), a frame that forms a screen is constituted by several subframes (SF) having different degrees of brightness to effect the gradation display.
In setting a voltage, when a final subframe SF is turned on in a given frame, the cell 3 of the subframe that should be turned on first in the next frame may not be properly displayed. This inconvenience is hereinafter called half tone noise, and its pattern of generation is shown in FIG. 8(a).
That is, referring to FIG. 8(a), the state where noise is generated is illustrated by using a pattern for selectively turning on the three kinds of subframes shown in FIG. 8(a) under the condition where one frame is constituted by four subframes SF1 to SF4, the first frame is displayed and, then, the second frame is displayed.
As a result, it was found that when the subframe 4 just before the quiescent period S4 in the first frame is turned on, the subframe that is turned on first in the succeeding second frame generates half-tone noise as in the pattern a and in the pattern b described in the comments column of FIG. 8(b).
That is, in the pattern a, the subframe SF4 in the first frame just before the quiescent period S4 is turned on causes the subframe SF1 that is turned on first in the second frame to generate half tone noise. In the pattern b, the subframe SF4 in the first frame just before the quiescent period S4 is turned on causes the subframe SF3 that is turned on first in the second frame to generate half tone noise.
In the pattern c, on the other hand, the subframe SF4 in the first frame just before the quiescent period S4 is not turned on, and the subframe SF1 that is turned on first in the second frame does not generate half tone noise.
In FIG. 8(a), the lateral bar (-) means that the subframe SF is the one that is not turned on.
From the results discussed above, it can be considered that in the above-mentioned plasma display device, the subframe SF4 is turned on and, hence, a large amount of wall charge used in the sustain discharge is held in the cell 3 during the quiescent period S4 resulting in the occurrence of half tone noise irrespective of the number of times of sustain discharge of the final subframe SF4 and, accordingly, the cell of the SF that is turned on first in the next frame is no longer capable of effecting normal address discharge and normal sustain discharge.
When the final subframe SF4 is not turned on, contrary to the above, no wall charge is held in the cell 3 during the quiescent period S4, and the half tone noise is not generated.
The object of the present invention is to provide a plasma display device which is capable of displaying a high quality picture without generating half tone noise in the succeeding frames irrespective of the arrangement or the turned-on state of the subframes in a preceding frame that is displayed, by removing defects inherent in the above-mentioned prior art.